The taller the better seems all set to be the protocol in the business of creating computer chips, even as a new research has found out that ‘high-rise’ units are able to provide increased performance at lower costs. A team of engineers from Stanford University led by an Indian-origin scientist will be showcasing how they work at the ‘IEEE International Electron Devices Meeting’ taking place in San Francisco this week.
This will be done through a paper which Subhasish Mitra, a professor of electrical engineering and computer science, and H.S. Philip Wong from Stanford are set to present at the gathering. They will be showcasing the architecture that will make these ‘high-rise’ chips possible.
About the question of adoption of this architecture by companies, Mitra has confidently said that their design and fabrication techniques are pretty much scalable. The research is at an early stage right now, but he has mentioned that with further development, the newly invented ‘high-rise’ architecture could lead to ‘computing performance that is much, much greater than anything available today.’
This new architecture works in such a way that layers of logic are placed atop layers of memory in order to create a tightly interconnected ‘high-rise’ chip. Thousands of nano-scale electronic elevators will toil between these layers to move data between them faster, and while using less power. The prototype of this project shows how to put logic and memory together into 3D structures which can easily be mass-produced.
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Like we said, this new ‘high-rise’ chip architecture is not just a run-of-the-mill concept, as its developers have made sure that it’s something that can be built on the assembly lines. Let us now see how it shapes up in the time to come.